Global interconnect delay has become a significant bottleneck in high speed circuits as technology scales. Power loss is also a significant issue.
FIG. 1 depicts a generalized layout for a field programmable gate array (FPGA) 100 on a single integrated circuit die 110. As indicated, the die 110 is approximately square and measures about 30 millimeters (mm.) (1.2 inches) on a side. Several logic array blocks 120 are located on the die. These blocks are interconnected by various signal paths 130 including high speed global routing networks.
In the early years of FPGAs, the signaling on the global networks was two-level (high and low) single-ended. To increase speed and accuracy, low voltage differential signaling was introduced to the global routing network. However, interconnect remains a problem that introduces substantial bottlenecks in routing.
Signaling also consumes substantial amounts of power, thereby imposing on the integrated circuit die both significant power requirements and significant issues in disposing of the heat generated by the signaling. The power lost by signaling is given by: P=Σ(Pr(Δ swing))×Δ swing×Cout×Vdd×fclk;
where Δ swing is the difference at the driver output between the successive voltage levels;
Pr (Δ swing) is the probability of switching from one voltage level to another, which in the case of conventional two-level signaling is ½;
Cout is the driver output capacitive load;
Vdd is the supply voltage; and
fclk is the clock frequency.